IDT Interface Chip TSI721A1-16GILV BGA-143

TSI721A1-16GILV PCIe2-to-S-RIO2 Interface 143-FCBGA (13x13)

SKU: 10000+ Category:

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IDT Interface Chip TSI721A1-16GILV BGA-143

 

PCIe Features

? PCIe 2.1 standard compliant
? 5/2.5 Gbaud link speed
? x4/x2/x1 link width
? 128- and 256-byte maximum payload
? Advanced error reporting
? Internal error reporting
? Lane reversal
? Automatic polarity inversion
? Dynamic port width: x4 drops to x1
? ECRC support
? INTx, MSI, and MSI-X support
? Single virtual channel, VC0
? Single traffic class, TC0
— Generates only PCIe posted/non-posted TLPs with TC0
— Generates only PCIe Cpl/CplD TLPs with TC matching their requests
— Accepts PCIe TLPs with any TC
? Four BARs
— Prefetchable BAR with 32- or 64-bit addressing for PCIe-to-S-RIO bridging
— Non-prefetchable BAR with 32- or 64-bit addressing for PCIe-to-S-RIO bridging
— Non-prefetchable BAR with 32-bit addressing for PCIe MWr to S-RIO doorbell bridging
— Non-prefetchable BAR with 32-bit addressing for Tsi721 internal register access
? Initial credit advertisement programmable through EEPROM
? Dynamic control of credits through registers
? Starvation prevention based on flow control credit updates
? Large buffers
— 12 KB/2 KB/12 KB input buffers for up to 127 posted/non-posted/completion TLPs
— 12 KB/2 KB/12 KB output buffers for up to 128 posted/non-posted/completion TLPs
? Debug features
— Slave analog loopback through a control register
— Slave loopback using TS1/TS2 ordered sets
— Master loopback
— Internal error reporting
— ECC protection on internal memories

S-RIO Features

? S-RIO 2.1 standard compliant
? 5/3.125/2.5/1.25 Gbaud link speed
? x4/x2/x1 link width
? 34-, 50-, and 66-bit addressing
? 16 destID filters
? 8 S-RIO flows
? 9-KB ingress buffer (32 x 288)
? 9-KB egress buffer (32 x 288)
? Lane reversal
? Lane polarity inversion

Serise: TSI721
Keyword: TSI721A1-16GILV
Datasheet: TSI721A1-16GILV?Avaliable
Part Number: TSI721A1-16GILV

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Part Number: TSI721A1-16GILV

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